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RM0008
Table 37.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
ADC2 external trigger regular conversion alternate function remapping (1)
Alternate function
ADC2 external trigger regular
conversion
ADC2_ETRGREG_REG = 0
ADC2 external trigger regular
conversion is connected to
EXTI11
ADC2_ETRGREG_REG = 1
ADC2 external trigger regular
conversion is connected to
TIM8_TRGO
1. Remap available only for high-density devices.
8.3.7
Timer alternate function remapping
Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping
possibilities are listed in Table 40 to Table 42 . Refer to AF remap and debug I/O
configuration register (AFIO_MAPR) .
Table 38.
TIM5 alternate function remapping (1)
Alternate function
TIM5_CH4
TIM5CH4_IREMAP = 0
TIM5 Channel4 is
connected to PA3
TIM5CH4_IREMAP = 1
LSI internal clock is connected to TIM5_CH4
input for calibration purpose.
1. Remap available only for high-density and connectivity line devices.
Table 39.
TIM4 alternate function remapping
Alternate function
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM4_REMAP = 0
PB6
PB7
PB8
PB9
TIM4_REMAP = 1 (1)
PD12
PD13
PD14
PD15
1. Remap available only for 100-pin and for 144-pin package.
Table 40.
TIM3 alternate function remapping
Alternate function
TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] =
“00” (no remap) “10” (partial remap) “11” (full remap) (1)
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
PA6
PA7
PB0
PB1
PB4
PB5
PC6
PC7
PC8
PC9
1. Remap available only for 64-pin, 100-pin and 144-pin packages.
Doc ID 13902 Rev 9
155/995
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